Modem interfaces for Integrated Circuit (IC) packages, chips, and other devices have ever-increasing terminal densities. Many modem IC devices have so many terminals so tightly clustered that it becomes difficult to construct mutually-segregated conductors to connect carrier lines to each terminal. Signal-carrying terminals and lines are particularly burdensome, since they must be segregated from each other as well as from power and ground lines. Signal lines on an IC device or carrier must have sufficient electrical isolation from other conductors that undesired coupling and leakage paths are avoided.
Terminals in a pattern are principally described by their locations (i.e., of the center point) and their shape (typically square or roundish, and ring-shaped for metal-lined through holes). Each may be coupled to other terminals in the same plane (e.g., a via coupled to a pad). Depending on the structure of circuitry connecting to a set of terminals off-plane, terminals may be categorized as no-connects, power terminals, ground terminals, and signal terminals for connecting to signal lines. The terminal configuration of a pattern is typically repeated in two or more parallel layers, each terminal in each layer coupling to a corresponding terminal on the parallel layer(s).
In this document, an "interface" is a configuration of conductors and dielectrics arranged to provide electrical coupling to an IC device. An interface generally comprises an inward routing (toward the device) and an outward routing (away from the device) in directions parallel to a reference plane. Most typically, routing on an IC device and the carrier on which it is mounted have a significant cost and technology differential. For this reason, routability of an interface in one direction (i.e., inward or outward) has a much larger cost impact on the system than routability in the other. Despite this, few interface designs to date depart from fully dense terminal grids with uniform circumferential spacing. These interfaces do not dislocate terminals but provide routability in less desirable ways such as adding layers.
A "pattern" of terminals most commonly comprises substantially all terminals on a surface of one given type, so terms like "via pattern" and "bond pad pattern" are customary. "Routability" of a pattern or inter-terminal zone refers to the context-dependent technical possibility of positioning routing lines so that all signals may escape (inward or outward) from a given pattern. The context of the routing comprises the number of routing layers, the routing line widths and clearances, the terminal sizes and required clearances, the shielding scheme, protections against ground bounce, and other design constraints known in the art.
Commonly used interface schemes for IC packages include Pin Grid Array (PGA), Ball Grid Array (BGA), and Land Grid Array (LGA). PGA packages have an array of pins that are inserted into through-hole pads in a Printed Circuit Board (PCB). BGA packages have an array of pads and are mounted by soldering these pads on the package directly to surface pads on the mount side of the PCB. LGA packages have an array of metal stubs and are mounted to the PCB in a clamp with a compressible interposer material placed between the package and the PCB. For PGA, BGA, and LGA packages the patterns of pads on the PCB (and in the case of LGA--the conductive pattern in the interposer) match the pattern of the pins or pads on the package. These package types can usually interface with a socket also, such as for testing.
IC dies typically connect to the substrate within the IC package using either wire bond or Flip-Chip technology. Flip-Chip is used for high pin count IC dies. The "pins" on a Flip-Chip die are called bump pads. As with the package array technologies, there is a matching pattern of pads on the package substrate. Interconnect on the package substrate is typically used to connect the pads on the substrate (connected directly to the IC die) to the pins, pads, or stubs on the surface of the package that gets inserted, soldered, or pressed to the PCB.
Most PGA, BGA, and LGA arrays use a square or staggered "gridded" terminal pattern. As the number of pins in IC's increase and with the need to keep these packages small, the spacing between package pins can be as small as 0.5 mm. Since these arrays can have as many as 60 pins on each side and because PCB design rules have minimum trace widths and clearances of 3-4 mils, typically, many PCB signal layers are required to be able to interconnect to the pins of the package. Line, terminal, and dielectric width rules exemplify conventional Design Rules used in the art to confirm a design's quality before construction. PCB designers assure compliance with Design Rules with software tools called Design Rules Checkers (DRC's). See U.S. Pat. Nos. 5,634,093 and 4,768,154. In FIG. 1 of the former patent, Design Rule File 2c has rules for clearances between various object pairings, and conformity of a given layout is confirmed by Wiring Pattern Checking Unit 5. In fact, DRC's can readily confirm that a given pattern complies with any requirement, criterion, or preference stated with sufficient particularity. This simplifies the pattern designer's task to a mere repositioning of terminals that cause a violation of a Design Rule.
To enable routing in highly dense IC packages, micro-via, blind via, buried via, staggered via, and other technologies have become more common. Similarly, additional layers in IC package substrates are required for interconnections to flip-chip dies. Technologies such as these substantially increase the cost of carrier manufacture, compromising product yields, performance, and reliability. The present invention allows the design of interfaces for high pin count IC devices such that the interface footprints can be small (typically allowing smaller packages), that the carrier can be designed with fewer layers, that more stringent design rules can be satisfied, and that the use of expensive manufacturing processes can be minimized.